A stacked memory device in which a plurality of memory chips each including a dynamic random access memory (DRAM) circuit are stacked so as to be connected to each other through Through Silicon Vias (TSVs) repeatedly performs a refresh operation at specific time intervals in order to avoid loss of a storage content (data) from a storage element of the DRAM circuit due to discharge. A discharge rate of electric charge from the storage element of the DRAM circuit becomes higher as the temperature becomes higher, so that it is desirable that a refresh interval of the refresh operation in the memory device is reduced and the execution frequency is increased as the temperature becomes higher.
In the stacked memory device, for example, temperature sensors are disposed in a logic chip in which an in-device logic circuit is disposed and in the plurality of memory chips, and the refresh operation is performed by setting the shortest refresh interval that is uniform for the whole memory in accordance with a memory block having the highest temperature based on measurement results by the temperature sensors. In addition, a technology has been proposed by which, in a stacked memory device in which a plurality of memory chips are stacked on a logic chip so as to be connected to the logic chip through TSVs, the maximum temperature of the memory device is determined based on a table of temperature distribution information when each circuit in the logic chip is operated, and a refresh operation is performed by setting a refresh interval based on the maximum temperature.
In a system having a memory device in the related art, since a transfer rate in the memory device has been low, transmission of a signal such as data has been able to be performed even when a processor and the memory device are mounted to be separated from each other at a certain distance. However, it has been started to mount a processor and a memory device to be close to each other because a stacked memory device, which improves a memory band in high performance computing (HPC) and network devices, has been standardized as a next-generation memory and an interface has been speeded up.
Power consumption and self-heat generating of the processor are increased due to the refinement of a process and the higher performance of the processor. A temperature difference occurs in the stacked memory device due to the influence of such self-heat generation of the circuit arranged in the periphery, however, the shortest refresh interval is set to even a part in which the temperature is low and it is only sufficient that the refresh interval is long, so that the execution frequency of the refresh operation is increased, resulting in increase in the power consumption of the stacked memory device.
The Following is a Reference Document. [Document 1] Japanese Laid-open Patent Publication No. 2015-41395.